Improving energy efficiency is one of the major design challenges in computing, especially in battery-operated and autonomous embedded and mobile systems. In many systems, a large amount of computation is devoted to algorithms for audiovisual processing, recognition, and communication that heavily utilize digital signal processing (DSP) architectures. In a recently awarded NSF grant on the Formal Synthesis of Low-Energy Signal Processing Systems Relying on Controlled Timing-Error Acceptance, Profs. Andreas Gerstlauer and Michael Orshansky propose a new strategy for reducing energy consumption in DSP circuits. Traditional design approaches based on worst-case margining are highly suboptimal. Instead, recognizing that DSP algorithms are characterized by an inherent notion of a quality floor set by quantization and compression artifacts, small quality losses can be traded, in a systematically controlled manner, for significant energy savings. Initial studies on common image processing kernels have shown that energy savings of 50% are possible while maintaining a high quality level.
Proposed research will generalize and automate the new design strategy. The goals of this project are two-fold: (i) to formally develop models and analysis techniques for controlled timing-error acceptance for specific input signal statistics and quality-energy budgets, and (ii) to develop a comprehensive synthesis flow that allows multiple designtransformation techniques to be applied for improving quality-energy trade-offs for a large class of algorithms that can generally tolerate a small amount of errors.