Prof. Jaydeep Kulkarni of Texas ECE has received a grant from the Semiconductor Research Corporation (SRC) to study advanced low power memory technology development. The research proposes "novel SRAM technology aimed at decoupling the conflicting low leakage power and low supply voltage design requirement using emerging nano-devices such as memristor and selector switches."
SRC is "a world class technology research consortium. With its highly regarded university research programs, SRC plays an indispensable part in the R&D strategies of some of industry's most influential entities."
Description of Research:
Static Random-Access Memory (SRAM) technology is the enabler of advanced CMOS logic technology scaling and has significant implications on continuation of Moore’s law. With rapid growth in data intensive computing, the need for large capacity SRAMs is growing across all product segments ranging from battery powered IoTs, to high performance Microprocessors to emerging machine learning accelerators. SRAMs employing minimum geometry transistors are susceptible to increased manufacturing process variations and typically limit the minimum operating voltage (Vmin) of the entire SoC affecting the product level power consumption. Current SRAM development approach is based on creating different flavors of SRAM bitcells targeted for either high Performance or extremely low power. As a result, advanced process development cost is increasing rapidly to achieve healthy yield targets for multiple SRAM-bitcell variants.
This research proposes novel SRAM technology aimed at decoupling the conflicting low leakage power and low supply voltage design requirement using emerging nano-devices such as memristor and selector switches. During the standby mode, the bitcell contents are retained by programming the memristors thereby completely cutting off the supply voltage of the underlying SRAM bitcell achieving zero standby mode leakage. This research if successful, can help semiconductor companies to simplify the SRAM development across multiple product segment and can pave a road for future energy efficient memory technologies for big data compute applications.