Sanjay Banerjee

Cockrell Family Regents Chair in Engineering #4

Dr. Sanjay Banerjee is the Cockrell Family Regents Chair Professor of Electrical and Computer Engineering and the Director of the Microelectronics Research Center in the Department of Electrical & Computer Engineering at The University of Texas at Austin.

He received his B.Tech from the Indian Institute of Technology, Kharagpur, and his M.S. and Ph.D. from the University of Illinois at Urbana-Champaign in 1979, 1981 and 1983 respectively, all in electrical engineering. As a Member of the Technical Staff, Corporate Research, Development and Engineering of Texas Instruments Incorporated from 1983-1987, he worked on polysilicon transistors and dynamic random access trench memory cells used by Texas Instruments in the world's first 4Megabit DRAM, for which he was co-recipient of the Best Paper Award, IEEE International Solid State Circuits Conference, 1986.

He has been Assistant Professor (1987-90), Associate Professor (1990-93), and Professor (1993-) at The University of Texas at Austin. He has over 530 archival refereed publications/talks, 7 books/chapters, and 26 U.S. patents. He has supervised over 40 Ph.D. and 50 MS students. He received the Engineering Foundation Advisory Council Halliburton Award, 1991, the Texas Atomic Energy Fellowship (1990-1997), Cullen Professorship (1997-2001) and the NSF Presidential Young Investigator Award in 1988. His recent awards include the Distinguished Alumnus Award, IIT (2005), Industrial R&D 100 Award (with Singh in 2004), ECS Callinan Award, 2003, IEEE Millennium Medal, 2000 and SRC Inventor Recognition Award, 2000. He is a Fellow of IEEE, Distinguished Lecturer for IEEE Electron Devices Society, and was the General Chair of the IEEE Device Research Conference, 2002. He is currently active in the areas of ultra high vacuum and remote plasma-enhanced chemical vapor deposition for silicon-germanium-carbon heterostructure MOSFETs and nanostructures. He is also interested in the areas of ultra-shallow junction technology and semiconductor device modeling.

Research Interests: 

MOS and nanostructure device modeling
UHVCVD for Si-Ge-C heterostructure devices
Ultra-shallow junction technology and process modeling


MER 1.606B
UTA 7.314


(512) 471-6730

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