Prof. Kulkarni and Prof. Dodabalapur Receive a SRC Grant to Develop 3-Dimensional Memory Technologies

Thursday, May 7, 2020 - 9:00am

Prof. Jaydeep Kulkarni and  Prof. Ananth Dodabalapur have a received a grant from the Semiconductor Research Corporation (SRC) to develop 3-Dimensional memory technologies.

With slowdown of transistor feature size scaling, the transistor density, performance, and power consumption in Integrated Circuits scale at a much slower rate compared to the historical technology scaling trends. Researchers are exploring alternative device technologies to meet the ever increasing demand for for high performance/energy efficient computing. Towards this goal, multiple 3-dimensional (3-D) integration technologies have been proposed to continue transistor scaling beyond the traditional 2-D scaling. While significant progress has been made in 3-D technologies, many challenges still exist due to introduction of new materials and/or complex process integration steps. Ideally, these Back-End-Of-Line (BEOL) transistors should be compatible with the existing silicon process technology, support low temperature processing, modest performance while consuming very low power, should have the ability to stack multiple devices vertically.

Moreover, with the emergence of Machine Learning/ Artificial Intelligence hardware accelerators, there is a growing need for large capacity memories to store large amount data to perform numerous neural network computations. As a result, significant die-area of modern hardware accelerators is occupied by embedded memories such as Static Random Access Memory (SRAM). Large capacity SRAMs can mitigate the off-chip data movement energy/latency cost enabling energy efficient computations. Furthermore, these SRAM bitcells having regular layouts are well suited for 3-D integration along with rest of the 2-D logic blocks.

In this research, Prof. Kulkarni and Prof. Dodabalapur plan to develop novel BEOL transistor technologies to realize low power, high density, 3-D stacked SRAM technologies which can potentially address energy efficient data storage needs of next generation Integrated Circuits. Thin-film transistors (TFTs) which can be processed under conditions appropriate for BEOL are promising for such applications.  Additionally, circuits based on new types of devices and more complex devices such as multi-gate devices can be incorporated in the back end, providing functionality that might not be conveniently available from silicon transistors.

TFT SEM

15nm Channel Length TFT SEM image

 

Thin Film Transistor

Thin Film Transistor: Device Structure